Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processing system that executes programs, such as, communication and multimedia programs. A processing system for such products may include multiple processors, complex memory systems using virtual memory hardware and techniques for storing programs and data, controllers, peripheral devices, such as communication interfaces, and fixed function logic blocks configured, for example, on a single chip. At the same time, portable products have a limited energy source in the form of batteries that are often required to support high performance operations from the processing system. To increase battery life it is desired to perform these operations as efficiently as possible. Many personal computers are also being developed with efficient designs to reduce overall energy consumption.
Virtual memory is a technique that presents a very large “virtual” memory space for program development and use while providing for the management of that virtual memory space in a complex memory system having less physical capacity. A complex memory system is conventionally organized in a hierarchy based on capacity and performance of cache memories, with the highest performance and lowest capacity cache located closest to the processor. For example, a level 1 instruction cache and a level 1 data cache would generally be directly coupled to the processor. A level 2 unified cache is in turn connected to the level 1 (L1) instruction and data caches. Further, a system memory is connected to the level 2 (L2) unified cache. The level 1 instruction cache commonly operates at the processor speed and the level 2 unified cache operates slower than the level 1 cache, but has a faster access time than that of the system memory. In addition, virtual memory cache subsystems may include translation look aside buffers (TLBs) to provide fast translations of virtual to physical memory addresses for both instructions in an instruction TLB (ITLB) and data in a data TLB (DTLB). Caches and TLBs generally utilize content addressable memories (CAMs) to store, for example, an address or portion of an address that would be used in the translation process. For TLBs, the CAM may store previously translated virtual page numbers. A virtual page number presented for translation would cause a TLB CAM address tag compare operation in parallel with all of the previously stored address tags. When a match is detected, the output of the TLB would be a physical page number that corresponds to the presented virtual page number. The physical page number is then concatenated with a page offset from the virtual address to be translated to generate the translated physical address that can then be used to address the caches in the memory hierarchy.
In a TLB, for example, to access a value stored in the TLB's CAM generally requires an effective address, such as generated by a base plus offset calculation, which is compared against address tags stored in the CAM. The operation is generally described as an A+B=K operation, where A+B is a virtual address and K is a virtual address or portion thereof that was previously stored in the address tags. Such A+B=K operations may be used in instruction and data caches and instruction and data TLBs. In one approach, an adder is utilized to generate the A+B value and then comparators are provided in a CAM to compare the A+B value with each of the CAM entries. However, this approach is slowed by having dependencies on the carry generation path in the adder.